1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device to minimize the formation of defects such as voids.
2. Description of the Related Art
As semiconductor devices have become increasingly integrated, the conductive patterns of the devices have become narrower and more closely spaced. Generally, the narrow patterns are contained in multi-layered structures in which interlayer dielectrics (or insulating interlayers) are used to electrically insulate adjacent patterns from each other, and in which contacts or vias are formed in the interlayer dielectrics to electrically connect upper and lower patterns. Each contact or via is formed by creating an opening through the interlayer dielectric (or the insulating interlayer) and by filling the opening with a conductive material.
In order to reliably form the vias or contacts, the interlayer dielectric should be uniform and dense and completely occupy the space between adjacent patterns. That is, the interlayer dielectric should be free of voids. However, as the design rule of the semiconductor device and the spacing between patterns are reduced, the interlayer dielectric must be formed in spaces having higher aspect ratios. This makes it difficult to form the interlayer dielectric without voids.
Additionally, in a semiconductor device having a size of less than about 100 nm, the pattern may be damaged while the interlayer dielectric in a narrow area between the patterns is etched to form a contact hole. Hence, a thick hard mask is used to protect the pattern when the interlayer dielectric is etched using a self-aligned contact (SAC) process. As a result, the aspect ratio of the portion between the patterns is further increased as a result of the presence of the hard mask.
A high density plasma enhanced chemical vapor deposition (HDP-CVD) process has been used to fill gaps having a high aspect ratio. However, in the case where the design rule of the semiconductor device has a critical dimension (CD) of less than about 0.2 μm, i.e. about 0.18 μm, the HDP-CVD process can result in the formation of voids or seams in the filled gaps.
Recently, a boro-phosphor silicate glass (BPSG) film has been adopted as an insulation film used to fill minute gaps. In this case, the BPSG film is formed and thermally treated to enhance a gap filling capacity thereof or to improve a flatness thereof. U.S. Pat. No. 6,368,957 (issued to Takuji Horio et. al.) discloses an example of a method for forming an insulation film using BPSG.
However, the method of using a BPSG film may not result in complete filling of a minute gap when the design rule of the semiconductor device is substantially reduced. The gap fill characteristic of the BPSG film can be enhanced by increasing the concentration of dopants such as boron (B), phosphorus (P), etc., but the resultant BPSG film may be easily etched during a wet etching process so that the BPSG film may not be sufficiently formed between adjacent contact holes. As a result, a bridge between adjacent contacts may occur so that a failure such as an electrical short of the semiconductor device may result when the contacts are formed.
FIG. 2 is a scanning electron microscopic image illustrating a semiconductor device in the case where an insulation film is generally formed employing a conventional gap filling process. When openings between conductive patterns 200 have aspect ratios of about 16:1, voids 220 are formed between the conductive patterns 200 after the insulation film is filled up in gaps between the conductive patterns 200. The voids 220 are formed even though the insulation film is formed by a re-flow process using BPSG having an excellent gap filling characteristic. After contacts are formed through the insulation film using conductive materials, bridges may be formed between the contacts, thereby causing electrical shorts between the contacts.